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| HD151TS304ARP Spread Spectrum Clock for EMI Solution REJ03D0020-0400Z (Previous ADE-205-691C(Z)) Rev.4.00 May.19.2003 Description The HD151TS304A is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution. Features Supports 10 MHz to 60 MHz operation. (Designed for XIN = 24 MHz and 48 MHz) 1 copy of clock out with spread spectrum modulation @3.3 V 1 copy of reference clock @3.3 V Programmable spread spectrum modulation (0.25%, 0.5%, 1.5% central spread modulation and spread spectrum disable mode.) * SOP-8pin * Pin to pin compatible with HD151TS304RP * * * * Key Specifications * * * * * * Supply voltages : VDD = 3.3 V0.165 V Ta = 0 to 70C operating range Clock output duty cycle = 505% Cycle to cycle jitter = 250 ps typ. Output slew rate = 0.8V/ns min. Ordering Information Package Type SOP-8 pin (JEDEC) Package Code FP-8DC Package Abbreviation RP Taping Abbreviation (Quantity) EL (2,500 pcs / Reel) Part Name HD151TS304ARPEL Note: Please consult the sales office for the above package availability. Rev.4.00, May.19.2003, page 1 of 12 HD151TS304ARP Block Diagram VDD GND CLKOUT XIN OSC XOUT R=1 M 1/n SSC Modulator SEL0 1/m Synthesizer SSCCLKOUT R=100 k Mode Control SEL1 R=100 k Pin Arrangement SSCCLKOUT 1 8 SEL1 VDD 2 7 CLKOUT GND 3 6 SEL0 XIN 4 5 XOUT (Top view) Rev.4.00, May.19.2003, page 2 of 12 HD151TS304ARP SSC Function Table SEL1 :0 00 01 10 11 Spread Percentage 0.5% 1.5% SSC OFF 0.25% Note: 1.5% SSC is selected for default by internal pull-up & down resistors. Clock Frequency Table XIN(MHz) 48 24 SSCCLKOUT(MHz) 48 *1 CLKOUT(MHz) 48*2 24*2 24*1 Notes: 1. With spread spectrum modulation. 2. Without spread spectrum modulation. Pin Descriptions Pin name GND VDD CLKOUT SSCCLKOUT XIN XOUT SEL0 SEL1 No. 3 2 7 1 4 5 6 8 Type Ground Power Output Output Input Output Input Input Description GND pin Power supplies pin. Normally 3.3 V. Normally 3.3 V reference clock output. Spread spectrum modulated clock output. Oscillator input. Oscillator output. SSC mode select pin. LVCMOS level input. Pull-up by internal resistor. (100 k). SSC mode select pin. LVCMOS level input. Pull-down by internal resistor (100 k). Rev.4.00, May.19.2003, page 3 of 12 HD151TS304ARP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage *1 Symbol VDD VI VO IIK IOK IO Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD+0.5 -50 -50 50 0.7 Unit V V V mA mA mA W C Conditions Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: VI < 0 VO < 0 VO = 0 to VDD Tstg -65 to +150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Supply voltage DC input signal voltage High level input voltage Low level input voltage Operating temperature Input clock duty cycle VIH VIL Ta Symbol VDD Min 3.135 -0.3 2.0 -0.3 0 45 Typ 3.3 -- -- -- -- 50 Max 3.465 VDD+0.3 VDD+0.3 0.8 70 55 Unit Conditions V V V V C % Rev.4.00, May.19.2003, page 4 of 12 HD151TS304ARP DC Electrical Characteristics Ta = 0 to 70C, VDD = 3.3 V5% Item Input low voltage Input high voltage Input current Symbol VIL VIH II Min -- 2.0 -- -- Typ -- -- -- -- Max 0.8 -- 10 100 Unit V V A VI = 0 V or 3.465 V, VDD = 3.465 V, XIN pin VI = 0 V or 3.465 V, VDD = 3.465 V, SEL0, SEL1 pins V / ns 20% - 80% pF mA SEL0, SEL1 XIN = 24 MHz, CL = 0 pF, VDD = 3.3 V Test Conditions Input slew rate Input capacitance Operating current CI 1 -- -- -- -- 7 4 4 -- DC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 0 to 70C, VDD = 3.3 V5% Item Output voltage0 1 Symbol Min VOH VOL IOH IOL 3.1 -- -- -- Typ -- -- -30 30 Max -- 50 -- -- Unit V mV mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.5 V VOL = 1.5 V Output current* Note: 1. Parameters are target of design. Not 100% tested in production. Rev.4.00, May.19.2003, page 5 of 12 HD151TS304ARP AC Electrical Characteristics / Clock Output & SSC Clock Output Ta = 25C, VDD = 3.3 V, CL = 15 pF Item Cycle to cycle jitter *1, 2 Symbol tCCS Min -- -- -- -- -- -- -- Typ | 250 | | 250 | | 250 | | 250 | | 250 | | 250 | | 250 | -- -- -- -- -- -- -- -- -- 50 40 33 -- -- Max | 300 | | 300 | | 300 | | 300 | | 300 | | 300 | | 300 | 24.2 48.7 24.3 48.8 24.6 49.4 24.2 48.7 -- 55 -- -- 60 2 Unit ps Test Conditions SSCCLKOUT, 24 MHz SSCCLKOUT, 48 MHz SSCCLKOUT, 24 MHz SSCCLKOUT, 48 MHz SSCCLKOUT, 24 MHz SSCCLKOUT, 48 MHz CLKOUT, 24 MHz & 48MHz Notes SSCOFF SEL1:0 = 10 Fig1 SSC= 0.25% SEL1:0 = 11 Fig1 SSC= 1.5% SEL1:0 = 01 Fig1 Fig1 SSCOFF SEL1:0 = 10 Output frequency *1, 2 23.8 47.3 23.7 47.2 23.4 46.6 23.8 47.3 MHz SSCCLKOUT, XIN = 24 MHz SSCCLKOUT, XIN = 48 MHz SSCCLKOUT, XIN = 24 MHz SSCCLKOUT, XIN = 48 MHz SSCCLKOUT, XIN = 24 MHz SSCCLKOUT, XIN = 48 MHz CLKOUT, 24 MHz CLKOUT, 48 MHz SSC= 0.25% SEL1:0 = 11 SSC= 1.5% SEL1:0 = 01 Slew rate *1 *1 *1 tSL 0.8 45 -- -- 10 -- V/ns % KHz MHz ms @48 MHz CLKOUT 0.4 V to 2.4 V Clock duty cycle Output impedance Spread spectrum *1 modulation frequency Input clock frequency Stabilization time Notes: *1,3 @48 MHz SSCCLKOUT 1. Parameters are target of design. Not 100% tested in production. 2. Cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. Rev.4.00, May.19.2003, page 6 of 12 HD151TS304ARP SSCCLKOUT (or CLKOUT) tcycle n tcycle n+1 t CCS = (tcycle n) - (tcycle n+1) Figure 1 Cycle to cycle jitter Rev.4.00, May.19.2003, page 7 of 12 HD151TS304ARP Application Information 1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The C2 decoupling capacitor shown should be a tantalum type. R1 SSCCLKOUT 1 8 SEL1 R2 VDD C2 C1 3 6 SEL0 2 7 CLKOUT TS300 Series GND GND 4 GND XIN (Crystal or Reference input) XOUT (Crystal or Not connection) 5 Notes: C1 = High frequency supply decoupling capacitor. (0.1 F recommended) C2 = Low frequency supply decoupling capacitor. (22 F tantalum type recommended) R1, R2 = Match value to line impedance. (22 Reference value) Figure 2 Recommended circuit configuration Rev.4.00, May.19.2003, page 8 of 12 HD151TS304ARP 2. Example Board Layout Configuration VDD (+3.3 V Supply) P FB 22 F G R1 SSCCLKOUT 0.1 F G 1 8 R2 7 CLKOUT G 3 6 4 5 Crystal connection or Reference input Note: Crystal connection or Not connection G Via to GND plane R1, R2 = Match value to line impedance. (22 Reference value) FB = Ferrite bead. Figure 3 Example Board Layout Rev.4.00, May.19.2003, page 9 of 12 HD151TS304ARP 3. Example of TS300 EMI Solution IC's Application Spread Spectrum Modulated Clock XIN XOUT TS30X SSC CLKOUT Ref. Clock 3.3 V CMOS level ref. Clock CPU & ASIC XTAL Memory Graphics System Cont. Fig 4 Ref. Clock Input Example Spread Spectrum Modulated Clock XIN XTAL XOUT TS30X SSC CLKOUT CPU & ASIC Memory Graphics System Cont. System BUS System BUS Fig 5 XTAL Ref. Clock Input Example Rev.4.00, May.19.2003, page 10 of 12 HD151TS304ARP Package Dimensions As of January, 2003 Unit: mm 4.90 5.3 Max 5 8 1 4 3.95 *0.22 0.03 0.20 0.03 1.75 Max 0.75 Max 6.10 - 0.30 + 0.10 1.08 0 - 8 + 0.67 0.14 - 0.04 + 0.11 1.27 0.60 - 0.20 *0.42 0.08 0.40 0.06 0.15 0.25 M *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-8DC Conforms -- 0.085 g Rev.4.00, May.19.2003, page 11 of 12 HD151TS304ARP Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.4.00, May.19.2003, page 12 of 12 |
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